In the deep submicron technology, the design of synchronous clocks is vital to the performance and reliability of integrated circuits in chip design. In a clock distribution network, the time taken for clock signals to reach different registers should be synchronized. This requires distributions of all clock signals in the clock distribution network. A clock signal, an input from an external clock source or an output from an internal clock generator, passes through the clock distribution network constituted by combinational logic units and interconnects to sequential logic units.
At present, many clock tree structures have been proposed in the industry, which can be summarized as: tree-trunk structure, mesh structure, symmetrical H-tree structure and balanced buffer-tree structure, etc. In the above-mentioned structures, the balanced buffer-tree structure has been widely used in digital circuits.
The existing clock distribution networks are mainly divided into two categories:
1. Tree-Type Clock Distribution Network
Please refer to FIG. 1. FIG. 1 is a structure diagram showing a conventional tree-type clock distribution network. As shown in FIG. 1, the clock distribution network presents a tree-like structure, and the clock signals spread from root to branches. The tree-type clock distribution network is the earliest used clock generation technology.
It has advantages like simple algorithm, low consumption of layout and wiring resources and low power consumption; it has disadvantages like relatively weak timing performance, strong timing variations, great influence of process variation on timing sequence and the resulting low predictability of the timing sequence in front-end design and back-end design processes.
2. Mesh-Type Clock Distribution Network
Please refer to FIG. 2. FIG. 2 is a diagram showing the conventional mesh-type clock distribution network. As shown in FIG. 2, the clock distribution network presents a mesh-like structure, and the timing sequence gets balanced in the whole network. The mesh-type clock distribution network is a rather new clock distribution technology.
It has advantages like small timing variations, low influence of process variations on timing sequence, good predictability in front-end design and back-end design, and relatively stable performance; it has disadvantages of requiring relatively more layout and wiring resources and consuming more power.